1. Technical Field
The present disclosure relates to a standard cell circuit, a semiconductor integrated circuit, and a semiconductor integrated circuit device.
2. Description of the Background Art
In recent years, increasing speed and functionality of digital circuits has led to speed-up and integration of semiconductor integrated circuit devices. As the circuit grows in size, layout of the semiconductor integrated circuit device is generally designed using a standard cell library.
A standard cell for automatic layout wiring, used for the standard cell library, includes a standard cell for multiple power supplies and a standard cell for a single power supply. A characteristic feature of the standard cell for multiple power supplies is that the standard cell includes a first power supply line and a second power supply line electrically insulated from the first power supply line, and the N-well is situated away from the whole peripheral boundary of the cell. In addition, the standard cell for a single power supply includes a power supply line connected to the first power supply line of the standard cell for multiple power supplies. Accordingly, even when the standard cell is arrayed adjacent to others in rows or columns, the N-well in the standard cell can be separated from the adjacent N-well of the standard cell.
FIG. 1A is a block diagram illustrating a configuration of a metal oxide semiconductor field effect transistor (MOSFET) formed according to a layout rule when a power supply voltage of 6.0 V is used. FIG. 1B is a block diagram illustrating a configuration of a MOSFET formed according to a layout rule when a power supply voltage of 1.8 V is used.
As illustrated in FIGS. 1A and 1B, a gate electrode Ag formed of polysilicon is formed on a positive channel (P-ch) region Ap corresponding to a P-channel type MOS transistor (pMOS transistor) and a negative channel (N-ch) region An corresponding to a N-channel type MOS transistor (nMOS transistor). Considering the withstand voltage of the gate electrode Ag, it is necessary for a width Wg of the gate electrode Ag to be wider as the power supply voltage increases. Accordingly, in general, as the power supply voltage increases, the layout area of the circuit also increases.
In the above-mentioned conventional standard cell for automatic layout wiring, as the layout area of the circuit that operates at the higher of the voltages supplied by the first power supply line or second power supply line increases, it becomes difficult to reduce the entire layout area of the standard cell for automatic layout wiring.